The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Mar. 08, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sangho Rha, Seongnam-si, KR;

Jongmin Baek, Suwon-si, KR;

Wookyung You, Suwon-si, KR;

Sanghoon Ahn, Goyang-si, KR;

Nae-In Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/288 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/0228 (2013.01); H01L 21/02178 (2013.01); H01L 21/02274 (2013.01); H01L 21/288 (2013.01); H01L 21/306 (2013.01); H01L 21/3212 (2013.01); H01L 21/7682 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76826 (2013.01); H01L 21/76829 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76849 (2013.01); H01L 21/76871 (2013.01); H01L 21/76877 (2013.01); H01L 23/5222 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 21/76885 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.


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