The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Nov. 20, 2017
Applicant:

Infineon Technologies Americas Corp., El Segundo, CA (US);

Inventor:

Robert T. Carroll, Andover, MA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/482 (2006.01); H01L 23/50 (2006.01); H01L 27/06 (2006.01); H01L 29/423 (2006.01); H02M 3/335 (2006.01); H01L 27/088 (2006.01); H02M 3/158 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/486 (2013.01); H01L 21/768 (2013.01); H01L 23/4824 (2013.01); H01L 23/495 (2013.01); H01L 23/498 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/49822 (2013.01); H01L 23/49861 (2013.01); H01L 23/50 (2013.01); H01L 24/17 (2013.01); H01L 27/0617 (2013.01); H01L 29/4238 (2013.01); H02M 3/33507 (2013.01); H02M 3/33576 (2013.01); H02M 3/33592 (2013.01); H01L 24/02 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 27/088 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/114 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/1161 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1415 (2013.01); H01L 2224/14104 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/17106 (2013.01); H01L 2224/29099 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81801 (2013.01); H01L 2924/00013 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1426 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3011 (2013.01); H02M 3/1588 (2013.01); Y02B 70/1466 (2013.01);
Abstract

According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.


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