The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Aug. 31, 2016
Applicant:

Aisin Aw Co., Ltd., Anjo-shi, Aichi-ken, JP;

Inventor:

Takanobu Naruse, Nishio, JP;

Assignee:

AISIN AW CO., LTD., Anjo-shi, Aichi-ken, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01); H01L 23/50 (2006.01); H05K 3/42 (2006.01); H01L 23/00 (2006.01); H01L 23/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/12 (2013.01); H01L 23/50 (2013.01); H01L 24/48 (2013.01); H05K 1/0262 (2013.01); H05K 1/0263 (2013.01); H05K 1/112 (2013.01); H05K 3/429 (2013.01); H05K 3/46 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main substrate that has a plurality of wiring layers and through holes, the surface layer power supply path supplying power to a semiconductor chip via an inner peripheral-side power supply terminal group and an outer peripheral-side power supply terminal group. The surface layer power supply path overlaps the inner peripheral-side power supply terminal group and the outer peripheral-side power supply terminal group as seen in the orthogonal direction, and is formed continuously so as to extend in a direction from a position at which the surface layer power supply path is connected to the inner peripheral-side power supply terminal group toward the outer peripheral side of the main substrate.


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