The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Jan. 30, 2019
Applicant:
Nanya Technology Corporation, New Taipei, TW;
Inventor:
Ting-Cih Kang, New Taipei, TW;
Assignee:
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/76852 (2013.01); H01L 21/76871 (2013.01); H01L 21/76898 (2013.01); H01L 23/53238 (2013.01); H01L 23/562 (2013.01);
Abstract
The present disclosure provides a through silicon via structure and a method for manufacturing the same. The through silicon via structure includes a semiconductor substrate, a shaping film, a conductive line, a barrier layer, and an insulating layer. The shaping film is disposed over a back surface of the semiconductor substrate, and is configured to maintain a planar formation of the semiconductor substrate. The conductive line is disposed through the shaping film and in the semiconductor substrate. The barrier layer surrounds the conductive line, and the insulating layer surrounds the barrier layer.