The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Dec. 11, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seok-Jin Cho, Seoul, KR;

Tae-Young Oh, Seoul, KR;

Jung-Hwan Park, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/44 (2006.01); G06F 11/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 29/44 (2013.01); G06F 11/1068 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 29/52 (2013.01);
Abstract

A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.


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