The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Jul. 12, 2018
Applicant:
Allegro Microsystems, Llc, Manchester, NH (US);
Inventors:
Nicolas Rafael Biberidis, Barcelona, ES;
Octavio H. Alpago, Ciudad de Buenos Aires, AR;
Nicolas Rigoni, Buenos Aires, AR;
Assignee:
Allegro MicroSystems, LLC, Manchester, NH (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G01R 33/07 (2006.01); G01R 33/09 (2006.01); G11C 29/44 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G01R 33/077 (2013.01); G01R 33/09 (2013.01); G06F 11/1068 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01); G11C 11/56 (2013.01);
Abstract
A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.