Refresh control circuit, semiconductor memory device, and refresh method thereof

Abstract

A semiconductor memory device includes: first to Nmemory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nnon-volatile memories that correspond to the first to Nmemory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Ncount values by counting a number of the memory sets used in the first to Nnon-volatile memories, and generating a redundant reset signal based on the first to Ncount values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.