The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Mar. 23, 2016
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventor:

Axel Aue, Korntal-Muenchingen, DE;

Assignee:

Robert Bosch GmbH, Stuttgart, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 1/00 (2012.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G03F 1/70 (2012.01); H01L 27/02 (2006.01); G03F 1/72 (2012.01);
U.S. Cl.
CPC ...
G06F 30/39 (2020.01); G03F 1/00 (2013.01); G03F 1/70 (2013.01); G06F 30/392 (2020.01); H01L 27/0207 (2013.01); G03F 1/72 (2013.01);
Abstract

A method for synthesizing a circuit layout, characterized by the following features: primary circuit functions are placed on the circuit layout; secondary circuit functions are placed on the circuit layout; at least one first mask is generated in such a way that the first mask reproduces the primary circuit functions and covers the secondary circuit functions when a semiconductor substrate is structured according to the circuit layout by way of the first mask; and the placement of the circuit functions takes place in such a way that at least one changed mask reproduces the primary circuit functions and the secondary circuit functions when the semiconductor substrate is structured according to the circuit layout by way of at least one second mask.


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