The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Dec. 22, 2017
Applicant:

Advanced Mechanical Technology, Inc., Watertown, MA (US);

Inventors:

Albert C. Drueding, Belmont, MA (US);

Gary M. Glass, Newton, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01L 5/16 (2020.01); A61B 5/00 (2006.01); A61B 5/103 (2006.01); A61B 5/11 (2006.01); G01L 5/161 (2020.01); G01L 25/00 (2006.01); G01G 19/44 (2006.01); G01G 21/23 (2006.01);
U.S. Cl.
CPC ...
G01L 5/16 (2013.01); A61B 5/1036 (2013.01); A61B 5/1038 (2013.01); A61B 5/112 (2013.01); A61B 5/4023 (2013.01); A61B 5/6887 (2013.01); A61B 5/7235 (2013.01); G01L 5/161 (2013.01); G01L 25/00 (2013.01); A61B 5/1116 (2013.01); A61B 2560/0223 (2013.01); A61B 2562/0247 (2013.01); G01G 19/44 (2013.01); G01G 21/23 (2013.01);
Abstract

A method of timing data sampling includes, in a data acquisition device, generating sampling intervals from a system clock of the data acquisition device, sampling data at the generated sampling intervals, and receiving start of frame (SOF) signals from a port, such as a USB port. For a selected number of SOF signals received, an actual number of system clock cycles is determined for a time interval corresponding to the selected number of SOF signals. The actual number of system clock cycles is compared to a nominal number of system clock cycles and a sampling interval is adjusted based on the comparison. The actual number of system clock cycles may be determined using a count-and-capture counter. The nominal number of system clock cycles may be calculated based on a nominal system clock rate and on a known SOF interval. Generating sampling intervals may include using a divide-by-N counter.


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