The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10701808 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 30, 2020

Filed:

Jun. 07, 2019
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Tomoyuki Akahoshi, Atsugi, JP;

Daisuke Mizutani, Sagamihara, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/00 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 1/16 (2006.01); H05K 1/18 (2006.01); H01L 23/02 (2006.01); H01L 23/48 (2006.01); H01L 23/50 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01G 4/12 (2006.01); H05K 3/46 (2006.01); H01G 4/33 (2006.01); H01L 49/02 (2006.01); H05K 3/00 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/162 (2013.01); H01G 4/12 (2013.01); H01G 4/1227 (2013.01); H01G 4/33 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 28/60 (2013.01); H05K 1/024 (2013.01); H05K 1/115 (2013.01); H05K 1/16 (2013.01); H05K 3/0026 (2013.01); H05K 3/422 (2013.01); H05K 3/423 (2013.01); H05K 3/46 (2013.01); H05K 3/4688 (2013.01); H01L 23/50 (2013.01); H05K 2201/093 (2013.01); H05K 2203/072 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/107 (2013.01);
Abstract

A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.


Find Patent Forward Citations

Akahoshi, Tomoyuki. (2020). Capacitor built-in multilayer wiring substrate and manufacturing method thereof (U.S. Patent No. 10701808). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10701808

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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