The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Sep. 24, 2015
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Luis Miguel Vaquero Gonzalez, Bristol, GB;

Suksant Sae Lor, Bristol, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/16 (2006.01); H04L 29/08 (2006.01); H04L 12/931 (2013.01); H04L 12/24 (2006.01); H04L 12/26 (2006.01); H04L 12/707 (2013.01); H04L 12/715 (2013.01); H04L 12/935 (2013.01);
U.S. Cl.
CPC ...
H04L 67/1097 (2013.01); H04L 41/0893 (2013.01); H04L 43/08 (2013.01); H04L 45/22 (2013.01); H04L 45/64 (2013.01); H04L 49/3009 (2013.01); H04L 49/356 (2013.01);
Abstract

A memory system that is an example of the present disclosure comprises a memory fabric and an overlay. The memory fabric comprises: a network of memory components interconnected by optical interconnects, and memory address spaces of the memory components are aggregated and exposed as if the network were a single memory resource. The memory fabric further comprises router modules to implement steps of a fabric routing protocol to route memory-addressing requests along paths to destination memory components in the memory fabric. The overlay increases resiliency of the memory system and comprises overlay nodes to receive and forward memory-addressing requests from client programs and to implement steps of an overlay routing protocol to selectively control routing of received memory-addressing requests, to destination memory components, either along paths determined according to the fabric routing protocol or along alternative paths via overlay nodes.


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