The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Sep. 28, 2018
Applicant:

Shenzhen Epostar Electronics Limited Co., Shenzhen, CN;

Inventors:

Yu-Hua Hsiao, Hsinchu County, TW;

Heng-Lin Yen, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); G06F 9/30 (2018.01); G06F 12/126 (2016.01); G06F 11/10 (2006.01); G11C 16/08 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1174 (2013.01); G06F 9/30018 (2013.01); G06F 9/30036 (2013.01); G06F 11/1012 (2013.01); G06F 12/126 (2013.01); G11C 16/08 (2013.01); H03M 13/116 (2013.01); H03M 13/1117 (2013.01); H03M 13/6502 (2013.01);
Abstract

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit.


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