The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2020
Filed:
Dec. 07, 2018
Texas Instruments Incorporated, Dallas, TX (US);
Amar Kanteti, Bangalore, IN;
Ankur Kumar Singh, Bangalore, IN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.