The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Apr. 29, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Shyamsunder Balasubramanian, Plano, TX (US);

Toshio Yamanaka, Plano, TX (US);

Toru Tanaka, Plano, TX (US);

Mayank Garg, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02P 29/02 (2016.01); H02P 6/08 (2016.01); H03K 5/134 (2014.01); H02P 6/12 (2006.01); H02M 1/08 (2006.01); H02M 1/32 (2007.01); H03K 17/12 (2006.01); H02P 29/024 (2016.01); H03K 17/0812 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H02M 1/08 (2013.01); H02M 1/32 (2013.01); H02P 29/0241 (2016.02); H03K 17/08122 (2013.01); H03K 17/122 (2013.01); H03K 17/6871 (2013.01);
Abstract

A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.


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