The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Oct. 27, 2017
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Xiaolong He, Beijing, CN;

Zhifu Li, Beijing, CN;

Guangcai Yuan, Beijing, CN;

Haijiao Qian, Beijing, CN;

Dongsheng Li, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/10 (2006.01); H01L 21/268 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1274 (2013.01); H01L 21/02667 (2013.01); H01L 21/02675 (2013.01); H01L 27/12 (2013.01); H01L 27/1229 (2013.01); H01L 29/10 (2013.01); H01L 29/6675 (2013.01); H01L 29/66765 (2013.01); H01L 29/786 (2013.01); H01L 29/78606 (2013.01); H01L 29/78663 (2013.01); H01L 29/78678 (2013.01); H01L 29/78696 (2013.01);
Abstract

It is provided a low-temperature polysilicon thin film transistor formed on a substrate, including: a gate electrode on the substrate; an active layer on the gate electrode, the active layer including a channel region, the channel region having a polysilicon region and amorphous silicon regions respectively on both sides of the polysilicon region; and an etch stop layer on the active layer. An orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the gate electrode on the substrate, and an area of the orthogonal projection the polysilicon region on the substrate is smaller than an area of the orthogonal projection of the gate electrode on the substrate. The orthogonal projection of the polysilicon region on the substrate is located within an orthogonal projection of the etch stop layer on the substrate.


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