The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2020
Filed:
Nov. 01, 2018
Applicant:
Rohm Co., Ltd., Kyoto, JP;
Inventors:
Kazuhisa Ukai, Kyoto, JP;
Koji Nigoriike, Kyoto, JP;
Assignee:
ROHM CO., LTD., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 8/14 (2006.01); G11C 17/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11266 (2013.01); G11C 7/06 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 8/14 (2013.01); G11C 17/10 (2013.01); H01L 27/11226 (2013.01);
Abstract
A nonvolatile semiconductor storage device includes a plurality of cell transistor pairs including a pair of cell transistors sharing a first node connected to a bit line or a source line, and a dummy gate line laid in parallel with gate lines of the cell transistors, the dummy gate line applying an off voltage to a dummy transistor between the cell transistor pairs. The gate lines and the dummy gate line may be laid at equal intervals. A plurality of impurity diffusion layers corresponding to the first node and second nodes of the cell transistors may be formed at equal intervals in a continuous active region.