The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Apr. 19, 2018
Applicant:

Teledyne Scientific & Imaging, Llc, Thousand Oaks, CA (US);

Inventors:

Alexandros Papavasiliou, Thousand Oaks, CA (US);

Adam Young, Westlake Village, CA (US);

Robert Mihailovich, Newbury Park, CA (US);

Jeff DeNatale, Thousand Oaks, CA (US);

Assignee:

Teledyne Scientific & Imaging, LLC, Thousand Oaks, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/76879 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01);
Abstract

A method of forming void-free, high aspect ratio through-substrate vias by 'bottom-up' electroplating. In one embodiment, the method requires providing a substrate, forming a dielectric layer on the substrate's bottom side, providing at least one perforation through the dielectric layer, forming a via hole through the substrate from its top side to the dielectric layer and over the perforations, forming an isolation layer on the sidewalls of the via hole, forming a metal seed layer on the bottom side of the dielectric layer, electroplating the seed layer such that all of the perforations are plugged, and electroplating up the via hole from the plugs to fill the via hole.


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