The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Dec. 05, 2016
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Laura Marie Caulfield, Woodinville, WA (US);

Mark Alan Santaniello, Redmond, WA (US);

J. Michael Andrewartha, Woodinville, WA (US);

John J. Siegler, Carnation, WA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/50 (2006.01); G01R 31/3183 (2006.01); G11C 29/02 (2006.01); G01R 31/30 (2006.01); G11C 29/10 (2006.01); G11C 5/14 (2006.01); G11C 29/04 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50 (2013.01); G01R 31/3004 (2013.01); G01R 31/318342 (2013.01); G11C 29/021 (2013.01); G11C 29/10 (2013.01); G11C 29/50004 (2013.01); G11C 5/14 (2013.01); G11C 5/147 (2013.01); G11C 16/30 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/5004 (2013.01); G11C 2029/5006 (2013.01);
Abstract

The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.


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