The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Apr. 24, 2018
Applicants:

Shimeng Yu, Tempe, AZ (US);

Rui Liu, Tempe, AZ (US);

Inventors:

Shimeng Yu, Tempe, AZ (US);

Rui Liu, Tempe, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/54 (2006.01); G11C 11/418 (2006.01); G11C 11/412 (2006.01); H03K 19/20 (2006.01); G06N 3/08 (2006.01); G06N 3/063 (2006.01); G06N 3/04 (2006.01); H01L 27/11 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/54 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G11C 7/1006 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); H01L 27/1104 (2013.01); H03K 19/20 (2013.01);
Abstract

A static random access memory (SRAM) bit cell and a related SRAM array are provided. In one aspect, an SRAM cell is configured to perform an XNOR function on a first input value and a second input value. In another aspect, a number of the SRAM cells can be employed to form an SRAM array for supporting deep neural network and machine learning applications. The SRAM cell is coupled to a word line(s) and an inverted word line(s) that collectively define the first input value. The SRAM cell causes a voltage and/or current difference between a bit line(s) and a complementary bit line(s) coupled to the SRAM cell. By customizing the SRAM cell to enable the XNOR function and forming a binary neural network based on the SRAM array, it is possible to effectively implement computing-in-memory (CIM) for deep neural network and machine learning applications.


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