The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Jun. 29, 2018
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Thomas Haener, Bellevue, WA (US);

Martin Roetteler, Woodinville, WA (US);

Krysta Svore, Seattle, WA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 10/00 (2019.01); G06F 7/487 (2006.01); G06F 7/48 (2006.01); H04L 9/08 (2006.01); H03K 19/195 (2006.01); G06F 7/485 (2006.01);
U.S. Cl.
CPC ...
G06N 10/00 (2019.01); G06F 7/48 (2013.01); G06F 7/485 (2013.01); G06F 7/487 (2013.01); G06F 7/4876 (2013.01); H04L 9/0852 (2013.01); H03K 19/195 (2013.01);
Abstract

Quantum algorithms to solve practical problems in quantum chemistry, materials science, and matrix inversion often involve a significant amount of arithmetic operations. These arithmetic operations are to be carried out in a way that is amenable to the underlying fault-tolerant gate set, leading to an optimization problem to come close to the Pareto-optimal front between number of qubits and overall circuit size. In this disclosure, a quantum circuit library is provided for floating-point addition and multiplication. Circuits are presented that are automatically generated from classical Verilog implementations using synthesis tools and compared with hand-generated and hand-optimized circuits. Example circuits were constructed and tested using the software tools LIQUi|and RevKit.


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