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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10699054 B1

PDFFull Text
Date of Patent:
Jun. 30, 2020

Filed:

Aug. 17, 2018

Standard cell library, integrated circuit including synchronous circuit, and computing system for designing the integrated circuit

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Bong-hyun Lee, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Attorney:

Harness, Dickey and Pierce, P.L.C.

Primary Examiner:

Dinh T Le

Int. Cl.
CPC ...
H03K 3/037 (2006.01); G06F 30/398 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/3312 (2020.01); G06F 30/34 (2020.01); G06F 30/333 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H03K 3/0372 (2013.01); G06F 30/333 (2020.01); G06F 30/34 (2020.01); G06F 2119/12 (2020.01);
Abstract

An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.

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