Variable rate display interfaces

Abstract

In an exemplary variable rate display interface, a high-speed reverse data transfer is enabled over plural lanes of a display serial interface (DSI) bus during blanking periods. Further increases in bandwidth of each high-speed reverse data transfer may be achieved by increasing DSI clock speed during the blanking periods. Since a display relies on a host clock to send reverse data, the frequency of the reverse data is increased, which effectively increases the bandwidth of reverse channel lanes. By increasing the reverse bandwidth over existing pins in the DSI bus, more data may be transferred to the host, including raw touch/stylus data rather than processed data. The raw data may then be processed by the host's relatively powerful processors. By shifting the processing to the host, the need for a powerful touch screen controller (TSC) and/or a powerful touch display driver integrated circuit (TDDI) may be avoided.