The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Oct. 03, 2017
Applicant:

GM Global Technology Operations Llc, Detroit, MI (US);

Inventors:

Kshitiz Swaroop, Delhi, IN;

Varun Agarwal, Karnataka, IN;

Biswajit Tripathy, Karnataka, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/337 (2020.01); B23K 9/095 (2006.01); G05B 19/418 (2006.01); B23K 11/11 (2006.01); B23K 11/25 (2006.01); B23K 11/24 (2006.01); B23K 31/12 (2006.01); B23K 101/00 (2006.01);
U.S. Cl.
CPC ...
B23K 9/0953 (2013.01); B23K 11/11 (2013.01); B23K 11/24 (2013.01); B23K 11/25 (2013.01); B23K 31/125 (2013.01); G05B 19/41885 (2013.01); B23K 2101/006 (2018.08); G05B 2219/32015 (2013.01); G05B 2219/45135 (2013.01); G06F 30/337 (2020.01);
Abstract

A computer-implemented method for reducing spot welds in a parameterized workpiece model includes generating a new design space (DS) from an original spot weld DS. The new DS includes a plurality of spot weld locations from the parameterized workpiece model with the original spot weld DS. The new DS is optimized to have a fewer number of spot weld locations than the original DS. The processor identifies a plurality of offending spot weld locations of the remaining spot weld locations in the new DS and a plurality of conforming spot weld locations of the remaining spot weld locations. The processor removes all but one optimized extension candidate from processor-selected groupings of welds while enforcing a minimum distance requirement. The processor outputs an inter-distance constrained parameterized workpiece model with an optimized extension candidate in each of the plurality of extended DSs to an operatively connected output processor.


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