The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Jan. 29, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Lalan Jee Mishra, San Diego, CA (US);

Richard Dominic Wietfeldt, San Diego, CA (US);

Radu Pitigoi-Aron, San Jose, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/40 (2006.01); G06F 13/42 (2006.01); H04L 25/49 (2006.01); H04L 1/16 (2006.01);
U.S. Cl.
CPC ...
H04L 12/40156 (2013.01); G06F 13/4291 (2013.01); H04L 1/1607 (2013.01); H04L 12/40032 (2013.01); H04L 25/4902 (2013.01); G06F 2213/0016 (2013.01);
Abstract

Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.


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