The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Nov. 30, 2018
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Dae Sung Kim, Gyeonggi-do, KR;

Chol Su Chae, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
H03M 13/116 (2013.01); G06F 11/1076 (2013.01); H03M 13/1171 (2013.01);
Abstract

A parity check matrix generator for generating a parity check matrix including non-binary cyclic permutation matrices may include: a first memory configured to store a first weight as location information on a non-binary cyclic permutation matrix within the parity check matrix; a second memory configured to store a second weight as cyclic strength of matrix elements of the non-binary cyclic permutation matrix; a third memory configured to store a third weight used to determine a size of a non-binary matrix element among the matrix elements of the non-binary cyclic permutation matrix; and a matrix generator configured to generate the non-binary cyclic permutation matrix by applying a non-binary value to matrix elements of 1's among matrix elements of a binary cyclic permutation matrix having a size corresponding to the non-binary cyclic permutation matrix and reflecting one or more of the first to third weights into the non-binary value.


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Quick Actions:

Kim, Dae. (2020). Parity check matrix generator, operating method thereof and error correction circuit using parity check matrix generated by the same (U.S. Patent No. 10693498). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10693498

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