Pll with lock-in frequency controller

Abstract

A PLL has a frequency comparator that is active during lock-in. It outputs a signal related to the difference between the oscillator frequency and a target frequency. It captures an initial phase and observes change in phase relative to the initial phase. Two ways of capturing the initial phase are provided. The frequency comparator can provide input signals for the loop filter and make the PLL act as a frequency-locked loop during lock-in. Alternatively, it can provide input signals for a search controller that may perform a binary or other search. The frequency comparator may wait one or more cycles of the reference clock signal to reduce noise, or it may set a threshold to eliminate some noise. It may signal that the oscillator frequency equals the target frequency when the threshold has not been exceeded after a timeout. The search controller may directly or indirectly control the PLL's oscillator.