The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Sep. 28, 2018
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, KR;

Inventor:

Kyu Jin Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/07 (2006.01); H03F 1/30 (2006.01); H03F 3/21 (2006.01); H03F 3/195 (2006.01); H03F 1/32 (2006.01); H03F 3/213 (2006.01); H03F 1/52 (2006.01);
U.S. Cl.
CPC ...
H03F 1/302 (2013.01); H03F 1/32 (2013.01); H03F 1/3223 (2013.01); H03F 3/195 (2013.01); H03F 3/211 (2013.01); H03F 3/213 (2013.01); H03F 1/52 (2013.01); H03F 2200/21 (2013.01); H03F 2200/222 (2013.01); H03F 2200/27 (2013.01); H03F 2200/318 (2013.01); H03F 2200/387 (2013.01); H03F 2200/426 (2013.01); H03F 2200/444 (2013.01); H03F 2200/451 (2013.01); H03F 2203/21103 (2013.01); H03F 2203/21127 (2013.01); H03F 2203/21139 (2013.01);
Abstract

A power amplifying apparatus includes a first bias circuit configured to generate a first bias current, a first amplification circuit, configured to receive the first bias current, amplify a signal input to the first amplification circuit through a first node, and output a first amplified signal to a second node, a second bias circuit, configured to generate a second bias current which has a magnitude different from a magnitude of the first bias current, and a second amplification circuit, connected in parallel with the first amplification, configured to receive the second bias current, amplify the signal input through the first node, and output a second amplified signal to the second node. The second amplification circuit is configured to output the second amplified signal with a third-harmonic component that has a phase offsetting a third-order intermodulation distortion (IM3) component included in the first amplified signal, based on the second bias current.


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