The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2020
Filed:
Aug. 06, 2019
Finisar Corporation, Sunnyvale, CA (US);
Luke A. Graham, Allen, TX (US);
Sonia Quadery, Allen, TX (US);
Deepa Gazula, Allen, TX (US);
Haiquan Yang, Mckinney, TX (US);
II-VI Delaware Inc., Wilmington, DE (US);
Abstract
A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.