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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10693231 B1

PDFFull Text
Date of Patent:
Jun. 23, 2020

Filed:

Jun. 04, 2018

Transmit/receive switching circuit

Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jeremy Dunworth, La Jolla, CA (US);

Aliakbar Homayoun, Alamo, CA (US);

Andrzej Partyka, Bedminster, NJ (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:

Seyfarth Shaw LLP/QUALCOMM Incorporated

Primary Examiner:

Nguyen T Vo

Int. Cl.
CPC ...
H01Q 5/335 (2015.01); H04B 1/44 (2006.01); H03F 1/02 (2006.01); H03F 1/56 (2006.01); H03F 3/21 (2006.01); H03F 3/68 (2006.01); H03G 1/00 (2006.01); H04B 1/525 (2015.01); H03H 7/48 (2006.01); H01Q 1/22 (2006.01); H01Q 21/28 (2006.01); H01Q 21/30 (2006.01); H01Q 1/24 (2006.01); H01Q 21/06 (2006.01); H04B 1/00 (2006.01);
U.S. Cl.
CPC ...
H01Q 5/335 (2015.01); H01Q 1/2283 (2013.01); H01Q 21/28 (2013.01); H01Q 21/30 (2013.01); H03F 1/0277 (2013.01); H03F 1/56 (2013.01); H03F 3/211 (2013.01); H03F 3/68 (2013.01); H03G 1/0088 (2013.01); H03H 7/48 (2013.01); H04B 1/006 (2013.01); H04B 1/44 (2013.01); H04B 1/525 (2013.01); H01Q 1/246 (2013.01); H01Q 21/062 (2013.01); H01Q 21/065 (2013.01); H03F 2200/27 (2013.01); H03F 2200/294 (2013.01); H03F 2200/405 (2013.01); H03F 2200/451 (2013.01);
Abstract

A transmit/receive switching circuit implementation reduces transmitting/receiving switching losses in a transceiver during different modes of operation. The implementation includes connecting a low noise amplifier and a power amplifier in accordance with a shunt configuration in the transceiver. The implementation also includes disabling the power amplifier to achieve a high impedance state by grounding an output stage bias and enabling the low noise amplifier and disabling one or more transistors connected to a path between the low noise amplifier and the power amplifier during a receive mode.

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