The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Mar. 04, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Shunsuke Kasashima, Yokkaichi, JP;

Jun Nishimura, Kuwana, JP;

Takamitsu Ochi, Kuwana, JP;

Hisashi Harada, Yokkaichi, JP;

Ayaha Hachisuga, Yokkaichi, JP;

Ayako Kawanishi, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11568 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11565 (2017.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/1037 (2013.01); H01L 21/0217 (2013.01); H01L 21/0262 (2013.01); H01L 21/02164 (2013.01); H01L 21/02274 (2013.01); H01L 21/02636 (2013.01); H01L 21/3065 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/32136 (2013.01); H01L 29/40117 (2019.08);
Abstract

A semiconductor memory device according to an embodiment includes: a substrate; a plurality of first gate electrodes; a first semiconductor film facing the plurality of first gate electrodes; and a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film. Moreover, this semiconductor memory device includes: a plurality of second gate electrodes; a second semiconductor film facing the plurality of second gate electrodes; and a second gate insulating film provided between the plurality of second gate electrodes and the second semiconductor film. Moreover, this semiconductor memory device includes: a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, and extends in a second direction; and a third gate insulating film provided between the third gate electrode and the first semiconductor film. Moreover, a thickness in a first direction of the third gate insulating film is larger than a width in the second direction of the first gate insulating film and the second gate insulating film.


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