The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Mar. 27, 2017
Applicant:

Sony Corporation, Tokyo, JP;

Inventor:

Kiyohisa Sakai, Kanagawa, JP;

Assignee:

SONY CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/16 (2013.01); H01L 25/00 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2223/6666 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

There is provided a semiconductor device that enables a semiconductor module that connects a wiring substrate and a semiconductor chip mounted on the wiring substrate via a circuit element and that has reduced a wiring length to improve transmission quality of signals or the like so as to achieve miniaturization of the semiconductor module. The semiconductor device includes a wiring substrate, a semiconductor chip disposed on an upper surface of the wiring substrate, a resin portion formed between the wiring substrate and the semiconductor chip, and a circuit element embedded in the resin portion. The circuit element includes a first terminal connected to wiring formed on the upper surface of the wiring substrate, and a second terminal connected to a bump provided on a lower surface of the semiconductor chip.


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