The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Oct. 25, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Da Hee Kim, Suwon-Si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/053 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/053 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49894 (2013.01); H01L 24/08 (2013.01); H01L 24/20 (2013.01); H01L 23/3128 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/12105 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1088 (2013.01); H01L 2924/10252 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/14 (2013.01); H01L 2924/145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A semiconductor package includes a semiconductor chip having a first surface on which connection pads are disposed and a second surface opposing the first surface; a connection member including a first insulating layer disposed on the first surface of the semiconductor chip, a wiring pattern disposed on the first insulating layer and having a top surface of which an edge is rounded, a via penetrating through the first insulating layer and electrically connecting the connection pads to the wiring pattern, and a second insulating layer disposed on the first insulating layer and covering the wiring pattern; and an encapsulant disposed on the connection member and encapsulating the semiconductor chip.


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