The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Jan. 16, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ki-Seok Oh, Seoul, KR;

Seong-Hwan Jeon, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 11/4096 (2006.01); G11C 11/4076 (2006.01); G11C 29/12 (2006.01); G11C 29/02 (2006.01); G11C 29/10 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/1006 (2013.01); G11C 7/1009 (2013.01); G11C 7/1045 (2013.01); G11C 7/1066 (2013.01); G11C 7/1069 (2013.01); G11C 7/1072 (2013.01); G11C 7/1093 (2013.01); G11C 7/1096 (2013.01); G11C 7/222 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/10 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 8/12 (2013.01); G11C 2207/108 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A method of operating a semiconductor memory device including a plurality of pins configured to transfer data and signals from/to an outside of the semiconductor memory device, a memory cell array and a control logic circuit to control access to the memory cell array. A write command synchronized with a main clock signal and data synchronized with a data clock signal are received from outside of the semiconductor memory device, the data is stored in the memory cell array based on a frequency-divided data clock signal, data is read from the memory cell array in response to a read command and a target address received from the outside of the semiconductor memory device, and the read data is transmitted to the outside of the semiconductor memory device selectively with a strobe signal generated based on a frequency of the main clock signal.


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