The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Mar. 25, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Young-Ho Na, Seoul, KR;

Young-Sun Min, Hwaseong-si, KR;

Dae-Seok Byeon, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/05 (2006.01); G11C 5/02 (2006.01); G11C 16/04 (2006.01); H01L 25/065 (2006.01); G11C 16/08 (2006.01); G06F 1/324 (2019.01); G06F 1/32 (2019.01); H05K 1/00 (2006.01);
U.S. Cl.
CPC ...
G11C 5/025 (2013.01); G11C 16/0441 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H01L 25/0657 (2013.01); G06F 1/32 (2013.01); G06F 1/324 (2013.01); H05K 1/00 (2013.01);
Abstract

A semiconductor package includes first through third memory chips. The first memory chip is arranged on a package substrate, the second memory chip is arranged on the first memory chip, and the third memory chip is arranged between the first memory chip and the second memory chip. Each of the first through third memory chips includes a memory cell array storing data, stress detectors, a stress index generator, and a control circuit. The stress detectors are formed and distributed in a substrate, and detect stacking stress in response to an external voltage to output a plurality of sensing currents. The stress index generator converts the plurality of sensing currents into stress index codes. The control circuit adjusts a value of a feature parameter associated with an operating voltage of a corresponding memory chip, based on at least a portion of the stress index codes.


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