The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Mar. 08, 2017
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Katsuya Anzai, Anpachi-cho, JP;

Hideki Kawada, Anpachi-cho, JP;

Hiroshi Matsuda, Gifu, JP;

Yukitada Iwasaki, Mizuho, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 3/3275 (2016.01); G09G 3/20 (2006.01); G09G 3/3266 (2016.01); G09G 3/3225 (2016.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/2096 (2013.01); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 3/3648 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2310/0232 (2013.01); H01L 27/3276 (2013.01);
Abstract

An electro-optical device includes first and second signal lines extending in directions intersecting each other on a component substrate, a pixel area including a pixel electrode disposed in correspondence with an intersection of the first and second signal lines, a signal output circuit disposed outside the pixel area and outputs a driving signal to the first signal line, and a connection wiring connecting the signal output circuit and the first signal line. An outer peripheral edge of the pixel area has a curved portion or a bent portion in a portion facing the signal output circuit, and the signal output circuit includes a plurality of circuit blocks arranged along the curved portion or the bent portion of the portion facing the signal output circuit with deviated between adjacent circuit blocks in the direction of extension of the first signal line and/or the direction of extension of the second signal line.


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