The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Dec. 13, 2016
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Anthony Nicholas Liguori, Bainbridge Island, WA (US);

Jason Alexander Harland, Seattle, WA (US);

Matthew Shawn Wilson, Bainbridge Island, WA (US);

Nafea Bshara, San Jose, CA (US);

Ziv Harel, Kibbutz Megiddo, IL;

Darin Lee Frink, Lake Tapps, WA (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/57 (2013.01); G06F 9/4401 (2018.01); G06F 21/44 (2013.01);
U.S. Cl.
CPC ...
G06F 21/575 (2013.01); G06F 9/4406 (2013.01); G06F 9/4416 (2013.01); G06F 21/44 (2013.01); G06F 21/57 (2013.01);
Abstract

Disclosed herein are techniques for maintaining a secure execution environment on a server. In one embodiment, the server includes a non-volatile memory storing firmware, a programmable security logic coupled to the non-volatile memory, an adapter device coupled to the programmable security logic, and a processor communicatively coupled to the non-volatile memory via the programmable security logic. The adapter device and/or the programmable security logic can verify the firmware in the non-volatile memory while holding the processor and/or a baseboard management controller (BMC) in power reset, release the processor and the BMC from reset to boot the processor and the BMC after the firmware is verified, and then disable communications between the processor and the BMC and deny at least some requests to write to the non-volatile memory by the processor or the BMC.


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