The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Sep. 06, 2018
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Michael R. Seningen, Austin, TX (US);

Ben D. Jarrett, Austin, TX (US);

Edward M. McCombs, Austin, TX (US);

Greg M. Hess, Mountain View, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/06 (2006.01); G11C 11/419 (2006.01); G06F 17/16 (2006.01); G11C 7/10 (2006.01); G11C 5/14 (2006.01); G11C 8/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 12/06 (2013.01); G06F 17/16 (2013.01); G11C 5/144 (2013.01); G11C 5/148 (2013.01); G11C 7/1006 (2013.01); G11C 8/06 (2013.01); G11C 11/419 (2013.01);
Abstract

A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.


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