The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Feb. 28, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Raghavendra Srinivas, Bangalore, IN;

Bharat Kumar Rangarajan, Bangalore, IN;

Rajesh Arimilli, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/3296 (2019.01); G06F 1/3225 (2019.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G11C 5/14 (2006.01); G06F 1/3206 (2019.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/263 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G11C 5/14 (2013.01);
Abstract

Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.


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