The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

May. 16, 2017
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Kentaro Enoki, Chiyoda-ku, JP;

Tsuyoshi Yoshida, Chiyoda-ku, JP;

Yasuhisa Shimakura, Chiyoda-ku, JP;

Eiji Yagyu, Chiyoda-ku, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/225 (2006.01); G02F 1/01 (2006.01); H04B 10/516 (2013.01); G02F 1/21 (2006.01);
U.S. Cl.
CPC ...
G02F 1/225 (2013.01); G02F 1/0121 (2013.01); H04B 10/516 (2013.01); G02F 2001/212 (2013.01); G02F 2201/12 (2013.01); G02F 2202/102 (2013.01); G02F 2202/20 (2013.01);
Abstract

A superposition circuitry superposes a dither signal on a reference DC bias voltage and outputs a resultant voltage as a bias voltage to an MZ modulator, during control of a driving voltage amplitude. During the control of the driving voltage amplitude to the MZ modulator, an amplitude setter determines, by varying the amplitude of an output voltage from an amplifier, a plurality of amplitudes of output curves from a synchronous detector, each of which is obtained by varying the reference DC bias voltage output from a bias controller, and the amplitude setter sets the amplification factor of the amplifier, based on an amplitude of the output voltage from the amplifier that corresponds to an amplitude satisfying a predetermined condition, out of the plurality of the amplitudes of the output curves from the synchronous detector.


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