The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Apr. 30, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Pradip Bose, Yorktown Heights, NY (US);

Alper Buyuktosunoglu, White Plains, NY (US);

Schuyler Eldridge, Ossining, NY (US);

Karthik V. Swaminathan, Mount Kisco, NY (US);

Yazhou Zu, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G06F 30/00 (2020.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318357 (2013.01); G01R 31/31704 (2013.01); G06F 30/00 (2020.01);
Abstract

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.


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