Asymmetric pulse width comparator circuit and clock phase correction circuit including the same

Abstract

A clock phase correction circuit includes: a first variable delay circuit suitable for delaying a second source clock to generate a third clock; a first pulse generation circuit suitable for generating a first pulse signal that is activated from an edge of a first clock to an edge of the third clock and generating a second pulse signal that is activated from the edge of the third clock to the edge of the first clock; and a first delay value adjustment circuit suitable for detecting whether a ratio of a pulse width of the first pulse signal to a pulse width of the second pulse signal is greater or less than 1:3 to produce a detection result and adjusting a delay value of the first variable delay circuit based on the detection result.