The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Sep. 27, 2018
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventor:

Keisuke Saito, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01M 10/46 (2006.01); H02J 7/00 (2006.01); H01M 10/44 (2006.01); H01M 10/48 (2006.01); B60L 3/00 (2019.01); B60L 58/21 (2019.01); H02J 7/02 (2016.01); B60L 53/20 (2019.01); B60L 58/10 (2019.01); H01M 10/42 (2006.01);
U.S. Cl.
CPC ...
H02J 7/0072 (2013.01); B60L 3/0046 (2013.01); B60L 53/20 (2019.02); B60L 58/10 (2019.02); B60L 58/21 (2019.02); H01M 10/425 (2013.01); H01M 10/44 (2013.01); H01M 10/48 (2013.01); H02J 7/0021 (2013.01); H02J 7/0026 (2013.01); H02J 7/0027 (2013.01); H02J 7/0031 (2013.01); H02J 7/0068 (2013.01); H02J 7/027 (2013.01); B60L 2240/547 (2013.01); B60L 2240/549 (2013.01); H01M 2010/4271 (2013.01); H02J 7/00304 (2020.01);
Abstract

Provided is a battery module including a battery part including one battery cell or a plurality of battery cells connected in series, first and second leads respectively led out from a positive electrode and a negative electrode of the battery part, a first FET in which the first FET is an N-channel type and a drain of the first FET is connected to the first lead and a source of the first FET is connected to a positive output terminal, a negative output terminal connected to the second lead, a pre-discharge circuit provided in parallel with a drain-source path of the first FET and is configured to raise a potential of the positive output terminal prior to an ON state of the first FET at discharging, and a forced OFF circuit configured to turn off the first FET by short-circuiting between a gate and the source of the first FET.


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