The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Jun. 20, 2016
Applicant:

Kabushiki Kaisha Nihon Micronics, Musashino-shi, Tokyo, JP;

Inventors:

Kazuyuki Tsunokuni, Tokyo, JP;

Tatsuo Inoue, Tokyo, JP;

Tomokazu Saitoh, Tokyo, JP;

Juri Ogasawara, Tokyo, JP;

Takashi Tonokawa, Tokyo, JP;

Takuo Kudoh, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/04 (2006.01); H01M 10/04 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 21/822 (2006.01); H01L 21/77 (2017.01);
U.S. Cl.
CPC ...
H01M 10/0431 (2013.01); H01L 21/77 (2013.01); H01L 21/822 (2013.01); H01L 21/8234 (2013.01); H01L 27/04 (2013.01); H01L 27/06 (2013.01);
Abstract

A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.


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