The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Aug. 21, 2018
Applicant:

Magnachip Semiconductor, Ltd., Cheongju-si, KR;

Inventors:

Jeong Hwan Park, Gumi-si, KR;

Seung Sik Park, Gumi-si, KR;

Ha Yong Yang, Cheongju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/36 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 21/304 (2006.01); H01L 21/02 (2006.01); H01L 29/45 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/739 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66348 (2013.01); H01L 21/02129 (2013.01); H01L 21/02271 (2013.01); H01L 21/26513 (2013.01); H01L 21/304 (2013.01); H01L 21/324 (2013.01); H01L 29/0619 (2013.01); H01L 29/0696 (2013.01); H01L 29/36 (2013.01); H01L 29/402 (2013.01); H01L 29/417 (2013.01); H01L 29/45 (2013.01); H01L 29/7396 (2013.01); H01L 29/7397 (2013.01); H01L 29/0821 (2013.01); H01L 29/0865 (2013.01); H01L 29/1004 (2013.01); H01L 29/1095 (2013.01); H01L 29/41708 (2013.01); H01L 29/41741 (2013.01); H01L 29/4236 (2013.01);
Abstract

A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.


Find Patent Forward Citations

Park, Jeong. (2020). Method of manufacturing power semiconductor device (U.S. Patent No. 10686051). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10686051

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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