The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Aug. 06, 2018
Applicant:

Panasonic Corporation, Osaka, JP;

Inventors:

Shinji Ujita, Osaka, JP;

Daisuke Shibata, Kyoto, JP;

Satoshi Tamura, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/78 (2006.01); H01L 21/82 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H01L 27/098 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/2003 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 27/098 (2013.01); H01L 29/42356 (2013.01); H01L 29/7787 (2013.01); H01L 29/7788 (2013.01); H01L 29/7789 (2013.01); H01L 29/7802 (2013.01); H01L 29/0623 (2013.01); H01L 29/1066 (2013.01); H01L 29/41741 (2013.01); H01L 29/41766 (2013.01); H01L 29/4238 (2013.01);
Abstract

A semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first opening penetrating the second nitride semiconductor layer; an electron transit layer and an electron supply layer which are formed along an upper surface of the second nitride semiconductor layer and a recessed surface of the first opening; a gate electrode disposed above the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer; a source electrode disposed to cover the second opening and electrically connected to the second nitride semiconductor layer; and a drain electrode disposed on a back surface of the substrate. The electron supply layer has a side surface formed along a side surface of the first opening. The gate electrode is not disposed on the side surface of the electron supply layer.


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