The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Mar. 12, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventor:

Kenichi Murooka, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2454 (2013.01); G11C 13/0004 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); G11C 2213/79 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01);
Abstract

According to one embodiment, a resistance change type memory includes: a semiconductor substrate having a first impurity concentration; a first interconnect extending in a first direction perpendicular to a surface of the semiconductor substrate; a second interconnect including a first semiconductor layer, the first semiconductor layer extending in a second direction parallel to the surface of the semiconductor substrate and having a second impurity concentration lower than the first impurity concentration; a memory layer between the first interconnect and the first semiconductor layer; a transistor including a second semiconductor layer between the first interconnect and the semiconductor substrate; and a third interconnect between the semiconductor substrate and the second semiconductor layer, and extending in the third direction.


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