IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10685989 B1

PDFFull Text
Date of Patent:
Jun. 16, 2020

Filed:

Jun. 29, 2018

Method for manufacturing display panel, display panel, and display device

Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Hefei, CN;

Inventors:

Xingfeng Ren, Beijing, CN;

Guoquan Liu, Beijing, CN;

Zhengwei Chen, Beijing, CN;

Assignees:

BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;

HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Hefei, CN;

Attorney:

Fay Sharpe LLP

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/52 (2006.01); H01L 21/4763 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/32 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1244 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/136286 (2013.01); H01L 27/1225 (2013.01); H01L 27/1259 (2013.01); H01L 27/1296 (2013.01); H01L 27/3279 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); H01L 27/3262 (2013.01); H01L 2251/5392 (2013.01); H01L 2251/568 (2013.01);
Abstract

A method for manufacturing a display panel, a display panel, and a display device are provided. The method includes: forming a plurality of gate lines and a common electrode line pattern on a base substrate; forming an insulating layer on the base substrate on which the plurality of gate lines and the common electrode line pattern are formed; forming a via hole on the insulating layer; and forming a metal conductive pattern on the base substrate on which the insulating layer is formed. The common electrode line and the common electrode connection block located on two sides of a gate line are electrically connected through a bridging structure in a conductive layer made of metal, which reduces the resistance of the bridging structure, so that the voltage uniformity throughout the common electrode line pattern which is bridged through the bridging pattern is high.

Find Patent Forward Citations

Loading…