The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Feb. 06, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Kwang Soo Kim, Hwaseong-si, KR;

Si Wan Kim, Hwaseong-si, KR;

Jun Hyoung Kim, Seoul, KR;

Kyoung Taek Oh, Osan-si, KR;

Bong Hyun Choi, Yongin-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 29/423 (2006.01); H01L 27/1157 (2017.01); H01L 29/06 (2006.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 29/0642 (2013.01); H01L 29/4234 (2013.01);
Abstract

A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region.


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