The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2020
Filed:
Sep. 26, 2014
Sunggil Kim, Yongin-si, KR;
Phil Ouk Nam, Suwon-si, KR;
Gukhyon Yon, Hwaseong-si, KR;
Sunghae Lee, Suwon-si, KR;
Woojin Jang, Suwon-si, KR;
Dongchul Yoo, Seongnam-si, KR;
Hunhyeong Lim, Hwaseong-si, KR;
Junggeun Jee, Seoul, KR;
Kihyun Hwang, Seongnam-si, KR;
Sunggil Kim, Yongin-si, KR;
Phil Ouk Nam, Suwon-si, KR;
Gukhyon Yon, Hwaseong-si, KR;
Sunghae Lee, Suwon-si, KR;
Woojin Jang, Suwon-si, KR;
Dongchul Yoo, Seongnam-si, KR;
Hunhyeong Lim, Hwaseong-si, KR;
Junggeun Jee, Seoul, KR;
Kihyun Hwang, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-do, KR;
Abstract
The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.