The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Jun. 08, 2016
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Sho Suzuki, Tokyo, JP;

Tsuyoshi Osaga, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0312 (2006.01); H01L 23/00 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 24/30 (2013.01); H01L 24/29 (2013.01); H01L 29/45 (2013.01); H01L 29/452 (2013.01); H01L 2224/29155 (2013.01); H01L 2224/3003 (2013.01); H01L 2224/30181 (2013.01); H01L 2224/30505 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01015 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A semiconductor substrate () has a front surface and a back surface that are opposite each other. A first metal layer () is formed on the front surface of the semiconductor substrate (). A second metal layer () for soldering is formed on the first metal layer (). A third metal layer () is formed on the back surface of the semiconductor substrate (). A fourth metal layer () for soldering is formed on the third metal layer (). The second metal layer () has a larger thickness than that of the fourth metal layer (). The first, third, and fourth metal layers () are not divided in a pattern. The second metal layer () is divided in a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer ().


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